1. Technical Field
The present invention relates to fabricating integrated circuit structures, and more particularly to a structure and method for electrically interconnecting prefabricated circuit chips.
2. Background Art
An example of a technique for fabricating an integrated circuit structure having a stepped interposer is described in U.S. Pat. No. 5,714,800 issued Feb. 3, 1998 to Thompson entitled INTEGRATED CIRCUIT ASSEMBLY HAVING A STEPPED INTERPOSER AND METHOD. This reference discloses a method of forming an integrated circuit assembly having a stepped interposer, an integrated circuit die, and an encapsulant. The stepped interposer is coupled to the die and provides contact regions free from encapsulant.
U.S. Pat. No. 5,598,033 issued Jan. 28, 1997 to Behien et al. entitled MICRO BGA STACKING SCHEME describes a stacking method for micro-BGA circuits.
U.S. Pat. No. 5,109,320 issued Apr. 28, 1992 to Bourdelaise et al. entitled SYSTEM FOR INTERCONNECTING INTEGRATED CIRCUIT DIES TO A PRINTED WIRING BOARD discloses a system for electrically and mechanically connecting an integrated circuit board to a solderless printed circuit board.
The publication WAFER INTERCONNECTIONS by Blum et al. in the IBM Technical Disclosure Bulletin, Vol. 32 No. 108, Mar. 1990 at page 276 discloses a silicon wafer interconnector based on liquid contacting.
The publication HIGH-PERFORMANCE TEST SYSTEM by Klink et al. In the IBM Technical Disclosure Bulletin, Vol. 33 No. 14, Jun. 1990 at page 124 discloses a silicon carrier that is metallized and brought into contact with a wafer.
Co-pending U.S. patent application Ser. No. 09/039962, filed Mar. 16, 1998 and entitled METHOD AND APPARATUS FOR INTERCONNECTING MULTIPLE CIRCUIT CHIPS discloses a method for forming tetragonal contacts for mechanically and electrically interconnecting integrated circuit chips.